1. Field of the Invention
This invention relates to the field of programmable logic devices, and more particularly relates to a method and system for the secure exchange of IP cores.
2. Description of the Related Art
Intellectual Property (IP) cores are sub-elements of a design that represent separate functions that can be included in overall designs to provide such functionality. IP cores for programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are increasingly complex and correspondingly expensive to develop and verify. Because creating IP cores requires such a significant investment, IP core vendors require a secure mechanism to control the distribution and delivery of such IP cores. Encryption is the primary tool used to provide secure delivery of an IP core to a deployed system. Traditionally, a secret encryption key is known to the IP vendor in advance of providing the IP core. The secret key is used to encrypt the configuration bitstream that implements the IP core. Special key registers within the FPGA are programmed with the vendor's secret key. When the FPGA powers up a hardware decryption engine, the key register data is used to decrypt the encrypted IP core into a standard FPGA bitstream. This bitstream is generated within the FPGA and configures the FPGA's resources (e.g., look-up tables (LUTs), routing resources, and the like). There are a number of limitations to such a mechanism. Among such limitations:
There are typically a limited number of key registers in a given PLD. Since all of the vendor keys need to be programmed in advance in such an architecture, “worst case” key storage must be designed into the device;
The vendor must expose their secret key to the EDA tools of their customer, at a minimum. The EDA tool is perceived as a trusted agent that only generates an encrypted bitstream.
Another limitation concerns the delivery path of the vendor's secret key to the deployed PLD. Presently, there is no entity existing that can program the key registers (e.g., in an FPGA in a design). Providing such an entity would be invasive because such an entity must be present in the manufacturing process and must not be observable while sending the vendor keys to the FPGA. It is conceivable that unscrupulous board vendors could monitor for the key as the key is communicated to the PLD. Loss of key data remains an inconvenience, but this can be mitigated using battery-backed storage and capacitors that address short term power loss to a deployed system. In the event of a vendor key being compromised, however, revoking existing keys and replacing them with a new secure key is so expensive as to be prohibitive. The situation is similar for non-volatile key storage—the vendor lacks an elegant mechanism to revoke the keys from a deployed PLD. Once again, there must be enough key storage for each possible vendor.
Moreover, IP vendors and other sources of design information currently tend to focus their development efforts on designs for the application-specific integrated circuit (ASIC) market. This is due, in large part, to the simple, reliable methods that are presently available to securely provide IP cores in such applications.
Thus, IP vendors are often reluctant to tailor their IP cores for use in PLDs because current methods for downloading the requisite IP core are less than robust. As a result, IP vendors lack the motivation necessary to optimize their designs for a given PLD architecture. ASIC-centric IP cores therefore typically perform poorly in a PLD, which further reinforces the need for designers and manufacturers to migrate to an ASIC-based approach quickly after initial prototype testing using PLDs.
The net result of the foregoing limitations is that the bitstream encryption facilities of currently available PLDs are only used by an end customer to protect their final application bitstream. Vendors of IP used within the customer's design are effectively frozen out of encrypting their IP independently of the customer application.
What is therefore desired is a technique that provides a method for third-party IP cores to be delivered securely for use in a PLD such as an FPGA. Such a technique should prevent access to/use of the subject IP core(s) by unauthorized parties. Such a secure method should also allow different IP vendors to safely deliver encrypted IP to a PLD. Furthermore, it is desirable to achieve this goal without requiring a device to be programmed with each of the required vendor keys in advance of deployment. An IP vendor should be free to define and revoke keys used to encrypt their IP, because such keys could only transmitted to the target device when required. The framework responsible for the encryption and delivery of that IP should prevent the vendor keys being exposed to either the customer or other IP vendors used in the customer's design. Moreover, such a technique should provide IP vendors an incentive to optimize for a given PLD architecture by providing the foregoing features in a transparent, controllable, and economic mechanism.